1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device process, more specifically, to a method for forming contact holes in the semiconductor integrated circuit device, which can avoid the problem of the failure of the alignment marks due to light reflection.
2. Description of the Prior Art
In the process for semiconductor integrated circuits such as DRAM, formation of contact holes plays an important role in the process techniques. Take DRAM as an example, the contact holes include bit line contact holes, substrate contact holes, gate contact holes and the like.
FIG. 1a is a schematic diagram showing a prior art DRAM structure to where contact holes are to be formed. In this drawing, positions where a bit line contact hole (CB), a substrate contact hole (CS), and a gate contact hole (CG) are to be respectively formed are shown. At the portion where the bit line contact hole CB is to be formed, reference number 10 indicates a silicon substrate, 11 indicates a barrier nitride layer, 12 indicates a bit line region, 13 indicates a dielectric layer filled between the bit line regions 12 and 14 indicates an oxide layer on the dielectric layer 13 and the bit line regions 12. The material of the dielectric layer 13 comprises BPSC; and the material of the oxide layer 14 comprises TEOS, for example. On the oxide layer 14, a thin conductive layer, which can be a poly-silicon layer 15, is formed. Finally, a photoresist layer 16 is formed to define the position where the bit line contact hole CB is to be formed. At the portion where the substrate contact hole CS is to be formed, the barrier nitride layer 11 is formed on the substrate 10. On the barrier nitride layer 11, the dielectric layer 13, oxide layer 14 and thin poly-silicon layer 15 are formed. Finally, the position where the substrate contact hole Cs is to be formed is defined by using the photoresist layer 16. At the portion where the gate contact hole CG is to be formed, on the substrate 10, a conductive layer such as a poly-silicon layer 17, and a gate metal layer 18, of which the material can be WSi, are formed. On the gate metal layer 18, a cap nitride layer 19 is formed. Then, the oxide layer 14 and the thin poly-silicon layer 15 are formed on the cap nitride layer 19. Finally, the position where the gate contact hole CG is to be formed is defined by using the photoresist layer 16.
After the structure of FIG. 1a is etched and the photoresist layer 16 is removed, the resultant structure is shown in FIG. 1b. As can be seen from this drawing, at the portion of the gate contact hole CG, the cap nitride layer 19 acts as an etch stop layer. Accordingly, the depth of the etched contact hole fails to reach the gate metal layer 18.
In order to remove the unnecessary portion of the cap nitride layer 19, a poly hard mask 21 is formed on the partial structure where the gate contact hole CG is to be formed, as shown in FIG. 2. Then, the predetermined portion of the cap nitride layer 19 is removed by etching, so that the gate contact hole CG can reach the gate metal layer 18. Then, the poly hard mask 21 is removed, as shown in FIG. 3.
However, the material of the poly hard mask has a large reflection to yellow light such that strong light reflection occurs in the processes of developing and imaging. Accordingly, aligning marks would fail, making it difficult to align the marks. Therefore, additional aligning marks are required for the steps of developing, etching and so on. As shown in the drawing, due to misalignment, the etching is difficult to be perfectly performed such that some residual is left in the contact hole. Accordingly, the profile of the contact hole is influenced.
Therefore, there is a need for a solution to overcome the problems stated above. The present invention satisfies such a need.